Test Programming for Power Constrained Devices

The conventional method of testing during wafer sort using an Automatic Test Equipment (ATE) is to provide fixed clock period to the circuit under test (CUT). This may lead to longer test times owing to large number of sequential elements in the design. Under such scenario, it is observed that the dynamic power dissipated during each test cycle varies based on the amount of signal transitions in the CUT. We propose an asynchronous test methodology to reduce test time, where each clock cycle is customized to dissipate the same amount of power. Simulation results using this methodology shows upto 45% reduction in test time with ISCAS‘89 benchmark circuits. To establish the test programming feasibility of the new methodology the Advantest T2000GS ATE of Auburn University Test Lab was used. Test time reduction of 38% was demonstrated for scan test of a circuit.